69
9152BINDCO02/10
ATA8743
18.2 Register Description
18.2.1
MCUCR MCU Control Register
The External Interrupt Control Register A contains control bits for interrupt sense control.
" Bits 1, 0 ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 18-1 on page 69. The value on the INT0 pin is sampled before
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
18.2.2
GIMSK General Interrupt Mask Register
" Bits 7, 3..0 Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
" Bit 6 INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the
External Interrupt Control Register A (EICRA) define whether the external interrupt is activated
on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an
interrupt request even if INT0 is configured as an output. The corresponding interrupt of External
Interrupt Request 0 is executed from the INT0 Interrupt Vector.
" Bit 5 PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT11..8 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT11..8 pins are enabled individually by the PCMSK1 Register.
Bit
7
6
5
4
3
2
1
0
0x35 (0x55)
PUD
SE
SM1
SM0
ISC01
ISC00
MCUCR
Read/Write
R
R/W
R/W
R/W
R/W
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Table 18-1. Interrupt 0 Sense Control
ISC01
ISC00
Description
0
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
1
The rising edge of INT0 generates an interrupt request.
Bit
7
6
5
4
3
2
1
0
0x3B (0x5B)
INT0
PCIE1
PCIE0
GIMSK
Read/Write
R
R/W
R/W
R/w
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
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